1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology and more particularly, to a semiconductor memory device including a voltage generation circuit.
2. Description of the Related Art
Typically, semiconductor memory devices receive a power supply voltage VDD and a ground voltage VSS from an external source, and generate internal voltages used for performing internal operations.
The voltages used in the Internal operations may include a core voltage VCORE supplied to a memory area, a high voltage VPP used to drive a word line or used in overdriving, a back bias voltage VBB supplied as a bulk voltage of an NMOS transistor of the core area, and the like.
Furthermore, the voltages used in the internal operations may include a cell plate voltage VCP used as a plate voltage of a memory cell capacitor, and a bit line precharge voltage VBLP used for precharging a bit line. In general, the cell plate voltage VCP and the bit line precharge voltage VBLP have a voltage level corresponding to one half of the core voltage VCORE (i.e., VCORE/2), and thus the cell plate voltage VCP and the bit line precharge voltage VBLP may be generated by using the core voltage VCORE.
As the degree of integration of a semiconductor memory device increases, the power supply voltage VDD is reduced. Accordingly, the internal voltages used in the semiconductor memory device are also reduced. Particularly, a decrease of the core voltage VCORE, which has a lower level than the power supply voltage VDD, may result in a decrease in the data sensing margin of the semiconductor memory device using the bit line precharge voltage VBLP (i.e., VCORE/2), in a low voltage (i.e., VDD) environment.
FIG. 1A is a block diagram illustrating a conventional voltage generation circuit of a semiconductor memory device.
Referring to FIG. 1A, the conventional voltage generation circuit includes a reference voltage generation unit 10 and a voltage driving unit 20. The reference voltage generation unit 10 may divide a voltage inputted through a core voltage terminal VCORE_ND to generate a reference voltage LVBLP. The voltage driving unit 20 may drive an output terminal according to the reference voltage LVBLP to generate a bit line precharge voltage VBLP.
FIG. 1B is a diagram of the reference voltage generation unit 10 shown in FIG. 1A.
Referring to FIG. 1B, the reference voltage generation unit 10 includes a voltage division section 12 and a voltage trimming section 14. The voltage division section 12 includes a plurality of resistors R1 to R6 connected in series between the core voltage terminal VCORE_ND and a ground voltage terminal VSS. The reference voltage LVBLP may be outputted from an intermediate node of the resistors R3 and R4.
The voltage trimming section 14 may adjust a division ratio determined by the resistors R1 to R6 to allow the reference voltage LVBLP to have a voltage level corresponding to one half of a core voltage VCORE (i.e., VCORE/2).
The voltage trimming section 14 may select a voltage level to be divided by the voltage division section 12 by using a switching circuit and particularly, may include fuses F1 to F6 coupled in parallel to respective resistors R1 to R6 of the voltage division section 12. That is, at a wafer level, the fuses F1 to F6 are programmed (i.e., blowing or rupture) through a test so that the reference voltage generation unit 10 may generate the reference voltage LVBLP to have a level of VCORE/2.
Accordingly, when a specific voltage is supplied through the core voltage terminal VCORE_ND, the reference voltage generation unit 10 may generate the reference voltage LVBLP having a level of VCORE/2, and the voltage driving unit 20 may drive the output terminal according to the reference voltage LVBLP to generate the bit line precharge voltage VBLP. That is, the bit line precharge voltage VBLP may be generated in cooperation with the core voltage terminal VCORE_ND.
FIG. 2 is a graph describing a data margin of a semiconductor memory device including the conventional voltage generation circuit shown in FIGS. 1A and 1B, in a low voltage environment.
Generally, in a semiconductor memory device, a bit line is precharged by the bit line precharge voltage VBLP before a read or write operation is performed. A bit line sense amplifier of the semiconductor memory device performs an operation for sensing and amplifying memory cell data transmitted through the bit line during the read or write operation. The bit line sense amplifier performs the amplification operation by using driving voltages, for example, the core voltage VCORE and the ground voltage VSS, supplied through a pull-up power line RTO and a pull-down power line SB, respectively.
In a low voltage environment, during the read or write operation, to ensure a data sensing margin for a data value “1”, a core-up driving mode is employed to supply a core-up voltage VCORE_UP higher than the core voltage VCORE to the core voltage terminal VCORE_ND. That is, in a normal driving mode, the core voltage VCORE is supplied through the core voltage terminal VCORE_ND, while in a core-up driving mode, the core-up voltage VCORE_UP is supplied through the core voltage terminal VCORE_ND.
Accordingly, when the semiconductor memory device enters a core-up driving mode, the bit line is precharged using the bit line precharge voltage VBLP, and then the core-up voltage VCORE_UP and the ground voltage VSS are supplied through the pull-up and pull-down power lines RTO, SB, respectively. The bit line sense amplifier may then perform an operation for sensing and amplifying memory cell data loaded on the bit line by using the core-up voltage VCORE_UP and the ground voltage VSS.
As described in FIGS. 1A and 1B, the bit line precharge voltage VBLP may vary depending on the voltage supplied to the core voltage terminal VCORE_ND, so that the bit line precharge voltage VBLP may increase according to the core-up voltage VCORE_UP in the core-up driving mode. Accordingly, as illustrated in FIG. 2, at an initial state of the core-up driving mode, even though a data sensing margin of a data value “1” is ensured, a data sensing margin of a data value “O” is not sufficient. Therefore, an operation error of the semiconductor memory device may occur.